The present invention relates to a frequency difference detection apparatus suitable to detect a shift, from a reference frequency, of a highly precise clock input to a network synchronization unit.
A frequency difference detection circuit shown in FIG. 2 is conventionally known. This circuit comprises a single PLL (Phase Locked Loop) 50, a phase difference detection unit 52, and a frequency difference detection unit 54, as described in, e.g., Japanese Patent Laid-Open No. 4-316213. The PLL 50 generates an output clock 202 based on an input reference clock 200 in response to this reference clock 200. At the same time, the PLL 50 detects the phase difference between the reference clock 200 and the output clock 202 and performs control to suppress the phase difference to zero, thereby outputting the output clock 202 phase-locked with the reference clock 200. More specifically, the PLL 50 generates the output clock 202 having a certain phase difference from the reference clock 200 and highly stably frequency-synchronized, phase-locked with the reference clock 200. The phase difference detection unit 52 detects the phase difference between the reference clock 200 and the output clock 202 and outputs the detection output to the frequency difference detection unit 54. The frequency difference detection unit 54 receives as time series data the phase difference detected by the phase difference detection unit 52 and analyzes this time series data, thereby detecting the shift of the reference clock 200 from a nominal frequency.
In the frequency difference detection circuit shown in FIG. 2, even when the phase difference between the reference clock 200 and the output clock 202 fluctuates within the phase error range of the PLL 50 in the frequency-synchronized, phase-locked state, the detection output from the phase difference detection unit 52 is averaged using a statistical method, and at the same time, the high stability of the PLL 50 is used, so that the variation in reference clock 200 can be absorbed for a long time of period.
In the conventional frequency difference detection circuit, however, the detectable frequency difference and detection time are limited by the steady-state phase error and follow-up characteristics of the PLL 50.